ltc1065isw资料 | |
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ltc1065isw |
file size : 116 kb
manufacturer:linear description:the cy7c1380d/cy7c1382d sram integrates 524,288 x 36 and 1,048,576 x 18 sram cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. all synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (clk). the synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (ce1), depth-expansion chip enables (ce2 and ce3[2]), burst control inputs (adsc, adsp, and adv), write enables (bwx, and bwe), and global write (gw). asynchronous inputs include the output enable (oe) and the zz pin. |
1pcs | 100pcs | 1k | 10k | ||
型 号:ltc1065isw 厂 家:linear 封 装:0529 批 号:smd/dip 数 量:2998 说 明: |
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运 费: 所在地: 新旧程度: |
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联系人:林浩/林妮 |
电 话:0755-82532799/82532766/83989559 |
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公司地址: 深圳市福田区佳和大厦b座1802室 门市部:华强广场 q2a114展销柜 |