max793ese资料 | |
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max793ese |
file size : 116 kb
manufacturer:maxim description:adsc write accesses are initiated when the following condi- tions are satisfied: (1) adsc is asserted low, (2) adsp is deasserted high, (3) ce1, ce2, ce3 are all asserted active, and (4) the appropriate combination of the write inputs (gw, bwe, and bw[a:d]) are asserted active to conduct a write to the desired byte(s). adsc-triggered write accesses require a single clock cycle to complete. the address presented to a[16:0] is loaded into the address register and the address advancement logic while being delivered to the ram core. the adv input is ignored during this cycle. if a global write is conducted, the data presented to the dqs and dqps is written into the corresponding address location in the ram core. if a byte write is conducted, only the selected bytes are written. bytes not selected during a byte write operation will remain unaltered. a synchronous self-timed write mechanism has been provided to simplify the write operations. |
1pcs | 100pcs | 1k | 10k | ||
型 号:max793ese 厂 家:maxim 封 装:0633 批 号: 数 量:5789 说 明: |
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运 费: 所在地: 新旧程度: |
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联系人:林浩/林妮 |
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