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| sa56004adp资料 | |
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sa56004adp |
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file size : 116 kb
manufacturer: description:differential output for the synthesizer. lvpecl interface levels. active high master reset. when logic high, the internal dividers are reset causing the true outputs foutx to go low, and the inver ted outputs nfoutx to go high. when logic low, the internal dividers and the outputs are enabled. asser tion of mr does not affect loaded m, n, and t values. lvcmos / lvttl interface levels. clocks in serial data present at s_data input into the shift register on the rising edge of s_clock. lvcmos / lvttl interface levels. shift register serial input. data sampled on the rising edge of s_clock. lvcmos/lvttl interface levels. controls transition of data from shift register into the dividers. lvcmos / lvttl interface levels. analog supply pin. selects between cr ystal or test inputs as the pll reference source. selects xtal inputs when high. selects test_clk when low. lvcmos / lvttl interface levels. test clock input. lvcmos / lvttl interface levels. crystal oscillator interface. xtal_in is the input. xtal_out is the output. parallel load input. determines when data present at m8:m0 is loaded into m divider, and when data present at n1:n0 sets the n output divider value. lvcmos / lvttl interface levels. determines whether synthesizer is in pll or bypass mode. lvcmos / lvttl interface levels. |
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| 1pcs | 100pcs | 1k | 10k | ||
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型 号：sa56004adp 厂 家： 封 装：0633 批 号：smd 数 量：3362 说 明： |
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运 费： 所在地： 新旧程度： |
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| 联系人：林浩/林妮 |
| 电 话：0755-82532799/82532766/83989559 |
| 手 机：13510168121/13725556003 |
| qq：496982847/351622092 |
| msn：linearic@hotmail.com |
| 传 真：0755-82532766 |
| email：maxim_zi@126.com |
| 公司地址： 深圳市福田区佳和大厦b座1802室 门市部：华强广场 q2a114展销柜 |
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