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si9185dmp-adj资料
si9185dmp-adj
 
file size : 116 kb
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description:the xilinx fzp cplds utilize the patented xpla (extended programmable logic array) architecture. the xpla architecture combines the best features of both pla and pal type structures to deliver high-speed and flexible logic allocation that results in superior ability to make design changes with fixed pinouts. the xpla structure in each logic block provides a fast 7.5 ns pal path with five dedicated product terms per output. this pal path is joined by an additional pla structure that deploys a pool of 32 product terms to a fully programmable or array that can allocate the pla product terms to any output in the logic block. this combination allows logic to be allocated effi- ciently throughout the logic block and supports as many as 37 product terms on an output. the speed with which logic is allocated from the pla array to an output is only 1.5 ns, regardless of the number of pla product terms used, which results in worst case tpd's of only 9 ns from any pin to any other pin. in addition, logic that is common to multiple out- puts can be placed on a single pla product term and shared across multiple outputs via the or array, effectively increasing design density.
 
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型 号:si9185dmp-adj
厂 家:
封 装:0610
批 号:dip/sop
数 量:4855
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