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| uc3172adwp资料 | |
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uc3172adwp |
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file size : 116 kb
manufacturer: description:the 3-state serial output for the a/d conversion result. data out is in the high-impedance state when cs is high and active when cs is low. with a valid chip select, data out is removed from the high-impedance state and is driven to the logic level corresponding to the msb value of the previous conversion result. the next falling edge of i/o clock drives data out to the logic level corresponding to the next most significant bit, and the remaining bits are shifted out in order with the lsb appearing on the ninth falling edge of i/o clock. on the tenth falling edge of i/o clock, data out is driven to a low logic level so that serial interface data transfers of more than ten clocks produce zeroes as the unused lsbs. |
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| 1pcs | 100pcs | 1k | 10k | ||
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型 号：uc3172adwp 厂 家： 封 装：0633 批 号：dip/sop 数 量：3650 说 明： |
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运 费： 所在地： 新旧程度： |
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| 联系人：林浩/林妮 |
| 电 话：0755-82532799/82532766/83989559 |
| 手 机：13510168121/13725556003 |
| qq：496982847/351622092 |
| msn：linearic@hotmail.com |
| 传 真：0755-82532766 |
| email：maxim_zi@126.com |
| 公司地址： 深圳市福田区佳和大厦b座1802室 门市部：华强广场 q2a114展销柜 |
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